A resistance-variable non-volatile element is hereinafter referred to as a “resistance variable element”. A semiconductor device including a silicon device has been progressed in device integration and lower electric power consumption by miniaturization in a scaling law known as Moore's law, and has been developed at a pace of “aiming for quadrupling integration every three years”. Recent years have seen a metal oxide semiconductor field effect transistor (MOSFET) with a gate length of 20 nm or less, which causes a rise in a cost of a lithography process and a physical limit on a device dimension. Hence, improvement of a device performance with an approach different from the conventional scaling law is being desired.
Examples of a rise in a cost of a lithography process include a rise in prices of a manufacturing apparatus and a mask set. In addition, examples of a physical limit on a device dimension include an operating limit and a dimensional variation limit.
In recent years, a rewritable programmable logic device called a field programmable gate array (FPGA) or a programmable logic device (PLD) has been developed, which is positioned as an intermediate between a gate array and a standard cell. The FPGA allows a customer to configure a circuit arbitrarily by himself/herself after manufacture of a chip, and purchase is available for one chip at minimum. A common FPGA, which often uses a static random access memory (SRAM) and a pass transistor (or a flash-type transistor) as a routing switch in a reconfigurable circuit, has a large chip area and consumes a large amount of electric power. In addition, it is necessary to program a chip one by one after manufacturing the chip, and as a result, there is a problem that a chip cost is high.
Consequently, when a certain number of chips once functionally verified by an FPGA are required, there is a case of using a method of reprinting the same logical operation function on an application specific integrated circuit (ASIC) (called hard copy, master slice, and the like). Since a circuit function of a hard copy is determined by a layout of a wiring and a via plug in a manufacture process, a programming process after manufacture of a chip is unnecessary, which enables cost reduction.
Methods for hard copy include two ways: (1) a method in which a layout of a reconfigurable circuit is used as is; and (2) a method in which a circuit layout is redesigned as an ASIC achieving the same function. In (1), although a chip cost is lowered by elimination of a programming process, electric power consumed by a chip is approximately equivalent compared to a reconfigurable circuit before hard copy. In (2), despite a cost increase due to ASIC design and a novel cost for a reticle set, there is a benefit of reducing a chip size and reducing electric power consumption.
On the other hand, as a method of reducing electric power consumption of an FPGA, an FPGA of a type including a resistance-variable element inside a multi-layered wiring layer has been studied, in which the resistance variable element can be used for a routing switch and a memory.
As for an FPGA of a type including a resistance-variable element inside a multi-layered wiring layer, examples of the resistance variable element include a resistance random access memory (resistance RAM (ReRAM)) using a transition metal oxide, a NanoBridge (Registered Trademark) using an ion conductor, and the like. The ion conductor is a solid in which ions can freely move by application of electric field or the like.
Non-patent literature 1 (NPL1) discloses, as a resistance variable element with high possibility of enhancing a degree of freedom in a circuit, a switching element using metal ion translocation and electrochemical reaction in an ion conductor. The switching element disclosed in NPL1 is constituted of three layers of an ion conductive layer, and a first electrode and a second electrode which are provided respectively in contact with two faces of the ion conductive layer. The first electrode among these has a role for supplying the ion conductive layer with metal ions. The second electrode does not supply any metal ions.
An operation of the switching element is briefly described. When the first electrode is grounded and negative voltage is applied to the second electrode, a metal of the first electrode becomes a metal ion and dissolves in the ion conductive layer. The metal ion in the ion conductive layer then precipitates as being a metal in the ion conductive layer, and the precipitated metal forms a metal crosslink connecting the first electrode with the second electrode. By electrically connecting the first electrode with the second electrode by the metal crosslink, a switch enters an ON state.
On the other hand, when the first electrode is grounded and positive voltage is applied to the second electrode in the ON state, part of the metal crosslink is disconnected. Accordingly, the electrical connection between the first electrode and the second electrode is broken, and the switch enters an OFF state. Note that there are changes in electrical properties before the electrical connection is completely broken, such as an increase in resistance between the first electrode and the second electrode and a change in inter-electrode capacity, so that the electrical connection is eventually broken. In addition, in order to turn the OFF state to an ON state, the first electrode may be again grounded and negative voltage may be applied to the second electrode.
NPL1 discloses a configuration and an operation of a two-terminal type switching element having two electrodes with an ion conductor interposed therebetween and controlling a conduction state therebetween.
By using a reconfigurable circuit using the resistance variable elements, a chip size is reduced and electric power consumption can be also reduced compared with a conventional FPGA.